FIG. 1 is a circuit diagram showing a general folding circuit.
This folding circuit 10 has a ladder resistor 11 generating a reference voltage, a plurality of amplification circuits D1 to D5 having alternately connected current output ends, and load resistors R1 and R2.
The ladder resistor 11 has a plurality of resistors R3 to R6 tandem connected between a supply terminal of a maximum reference voltage Vrt and a supply terminal of a minimum reference voltage Vrb. From the respective nodes between the resistors and the above two supply terminals, a plurality of reference voltages Vrb, Vr1, Vr2, Vr3, and Vrt having sequentially changing values are output.
Each of the plurality of amplification circuits D1 to D5 compares an input voltage Vin with the reference voltage Vr (maximum reference voltage Vrt, minimum reference voltage Vrb, or reference voltage Vri (i=1, 2, 3)) and outputs a current (pulls a current from the output end) in accordance with a difference between the input voltage Vin and the reference voltage Vr.
FIG. 2 is a diagram showing an example of the circuit of the amplification circuits.
Each of the amplification circuits D1 to D5 is configured by, as illustrated, two NMOS transistors 12a and 12b forming a differential pair, and one current source 13. A voltage of an input signal (input voltage Vin) is applied to a gate of the NMOS transistor 12a, and the reference voltage Vr is input to a gate of the other NMOS transistor 12b. Sources of the NMOS transistors 12a and 12b are connected to each other and biased by a current flowing in the current source 13.
When a differential pair (amplification circuit) is biased by the current source 13 in this way, an input/output characteristic thereof becomes as shown in FIG. 3.
In the configuration of FIG. 1, when considering this input/output characteristic (FIG. 3), each time an amplification circuit exceeds the reference voltage Vr, the transistor pulling in the current in the differential pair is switched from the NMOS transistor 12b side to which the reference voltage Vr is applied (hereinafter referred to as a “positive phase output side”) to the NMOS transistor 12a side to which the input voltage Vin is applied (hereinafter referred to as an “inverse phase output side”) as shown in FIG. 2. By this switching of the output current (steering), folded waves having sequentially different values of reference voltages Vr as threshold values are generated.
Next, an explanation will be given of the generation of folded waves by an example of use of five amplification circuits (FIG. 1). In the amplification circuits D1 to D5, a notation “−” represents that a terminal side corresponding to the input terminal is the inverse phase output side, and another notation “+” represents that a terminal corresponding to the input terminal is the positive phase output side.
First, in the case where the relationship between the input voltage Vin and the minimum reference voltage Vrb is the input voltage Vin<Vrb, the outputs of all amplification circuits D1 to D5 output the output currents Io from the positive phase output side. For this reason, when the current flowing in the load resistor R1 (load current) is defined as Ir1 and the current flowing in the load resistor R2 (load current) is defined as Ir2, the following equations (1-1) and (1-2) stand:[Equations 1]Ir1=3Io  (1-1)Ir2=2Io  (1-2)
Next, when the input voltage Vin exceeds the minimum reference voltage Vrb and is less than the next reference voltage Vr1 (Vrb<input voltage Vin<Vr1), by the input voltage Vin exceeding the minimum reference voltage Vrb supplied to the amplification circuit D1, the amplification circuit D1 steers the output current Io thereof from the positive phase output side to the inverse phase output side, and at this time, the load currents Ir1 and Ir2 flowing in the load resistors R1 and R2 are changed as in the following equations (2-1) and (2-2):[Equations 2]Ir1=2Io  (2-1)Ir2=3Io  (2-2)
Next, when the input voltage Vin exceeds the reference voltage Vr1 and is less than the next reference voltage Vr2 (Vr1<input voltage Vin<Vr2), by the input voltage Vin exceeding the reference voltage Vr1 connected to the amplification circuit D2, the amplification circuit D2 steers the output current Io thereof from the positive phase output side to the inverse phase output side, at this time, the load currents Ir1 and Ir2 flowing in the load resistors R1 and R2 are changed as in the following equations (3-1) and (3-2):[Equations 3]Ir1=3Io  (3-1)Ir2=2Io  (3-2)
Hereinafter, whenever the input voltage Vin sequentially exceeds the reference voltages Vr2 and Vr3, the amplification circuits D3, D4, and D5 steer the output currents Io thereof from the positive phase output side to the inverse phase output side. Thus, folded waves shown in FIG. 4 are generated.
In the folding circuit, as explained before, the change of the input signal increases by exactly the number of folding, therefore, the input band tends to become low. For this reason, a track/hold circuit (T/H) stopping the change of input signal in synchronization with a control clock is often provided at the input stage. Due to this, an input band can be easily extended up to a band of the T/H.
On the other hand, the amplification circuits generating the folded waves are circuits of continuous systems, therefore, it is generally known that these circuits are very weak against a response to a large amplitude. A major reason of this is that the bias current is completely steered by applying excessive input to the differential pair configuring the folding circuit, and one side transistor cuts off.
With respect to such a problem, the technique as in Non-Patent Document 1 solves the problem and achieves high speed response.
This approach is, as shown in FIG. 5, intended that improvement of a recovery time of an amplification circuit by providing a switch 14 at an output end of the amplification circuit generating a folded wave, turning on the switch for only a track period of a track/hold circuit (T/H), and resetting the output end. The fact that the speed becomes five times faster than the conventional technology by this is described in Non-Patent Document 1.
Non-Patent Document 1: “An 8b 600 MS/s 200 mW CMOS Folding A/D Converter Using an Amplifier Preset Technique”, Govert Geelen et al., ISSCC04 Digest of Technical Paper, 14.2, 2004 Feb.